Test systems often generate signals that can be applied in parallel to multiple devices under test in order to reduce the amount of time needed to test such circuits. Similarly, signals from multiple devices under test can be read in parallel in order to decrease testing time. Different attempts have been made in the past to try to increase parallelism in a test system. Each approach has its benefits and drawbacks. For example, some approaches are: address fan-out using switches, data fan-out using switches, address wire-or, and data wire-or.
Address Fan-Out Using Switches:
One method to increase parallelism has been to take an address drive channel from a tester and connect it to multiple devices using switches (typically mechanical relays) to provide isolation. In most cases the switches sit between the test head and the device under test (DUT) load board or probe card. In some cases they are designed on the probe card itself. Although this approach presents a simple solution, there are multiple drawbacks:
Mechanical relays are bulky and prone to failure. Furthermore, downtime on a system can be a big problem.
In addition, signal performance can be affected in multiple ways. For example, solid state switches have ON resistance and capacitance which will limit the signal performance. This can be tolerated for low frequency testing; however, it is insufficient for high frequency testing. Also, broadcasting a tester signal to multiple DUTs via a transmission line split (assume one pin electronics (PE) line being split into multiple lines) creates severe intrinsic impedance mismatches if the lines are not balanced. Since a PE channel is typically source matched, multiple reflections are seen coming back for the DUTs when this configuration is used. If the branches are balanced (e.g., a 50 ohm line splitting into two 100 ohm lines), then the reflections coming back would cancel out at the split point. The un-balance could occur also if one of the DUTs is not present or if the lines are not length matched. Additionally, it is quite difficult to build high impedance lines using either strip line or micro-strip. To get high impedances either very skinny traces or very thick boards are required. Neither skinny traces nor thick boards are good for manufacturing. Thus, unbalanced lines can be produced in the manufacturing process, which causes an impact on timing accuracy.
If the lines are actually balanced (e.g., a 50 ohm line going into two 100 ohm lines) and one DUT fails. Then, a switch will need to be opened for the failed device. As a result, the 50 ohm line will be going into a single 100 ohm line. This will cause multiple reflections between the DUT and the point where the line splits.
A fanout greater than 2× becomes increasingly difficult due to printed circuit board (PCB) limitations. For example a 4× fanout would require fanning out a single 50 ohm line trace into 4 200 ohm traces. Moreover, testing performance will change as a function of how many DUTs are connected to the fanout lines.
An increase in parallelism does occur with fanout. For example, one could test two 32 pin devices (each having 8 data pins) using 2*8+24=40 pins. In comparison, if there were no address sharing, one would need 64 pins. A net gain of 64/40=1.6 or 60% gain in parallelism.
Data Fan-Out Using Switches:
Another approach to increasing parallelism has been to employ passive switches for data fan-out. Data fan-out produces further complications. Data fan-in/fan-out has the same issues as Address fan-out with the addition of:
Parallelism—When data is shared between DUTs, one needs to be able to independently control each DUT to be able to individually enable their I/O and drive back to the tester. The following net gain in parallelism is achieved. Using the same example as before, to test two 32 pin devices (each having 8 data pins), one would need 33 channels assuming one independent control to serially enable each device for read. A net gain of 64/33=1.94 or 94% gain in parallelism.
Test Time Overhead—Since one needs to read one device at a time, some test time overhead will be incurred. For example if the total read time of a given test program is 30% of the overall test time, then when performing all reads serially, the total test time for four DUT would increase to 0.7 (other)+0.3*2 (reads)=1.3 or 130% test time. Each DUT then causes a 30/2=15% TTO (test time overhead).
Address Wire-OR
Wire-OR configurations can be beneficial in that they require little or no additional circuits on the tester side. On any system in the market, a user can typically implement a wire-OR socket board or probe card. Depending on the desired speed and timing accuracy, a 1:2 or 1:3 or 1:4, etc. could be implemented. Also, there are a couple of variations: one could wire-OR only the driver outputs (Address/Control) and keep the data one to one, or one could wire-OR everything. Wire-OR also has its associated drawbacks.
Electrical Issues—Using a wire-OR configuration on a Tester I/O between multiple devices creates multiple electrical issues. First, it is not possible to isolate a bad device (for example a shorted input would cause all devices tied together to that channel to fail. But, one cannot tell which device is causing the failure.
In wafer sort a bad device would cause other good devices to be marked as bad. And in this case, it is much more difficult to re-test. Therefore, this becomes a yield loss
It is also not possible to perform independent parametric testing on each DUT input or I/O in a wired-OR configuration. This is true even if one serializes the tests. Signal Performance—Use of Wired-OR degrades timing performance due to the transmission line sharing by multiple loads. Most if not all device inputs are high impedance. Since most tester's termination method is to use 50 ohm back-matching as soon as one starts driving multiple DUTs with a single tester channel, one will see discontinuities and reflections that depending on the topology might significantly degrade the timing performance of the signals being driven into a DUT (unless the lines are perfectly balanced).
Parallelism—The same analysis as in Address sharing using switches can be applied to a wire-or address configuration.
Test Time Overhead—Test time overhead is not an issue in this case assuming the data is connected one-to-one to the tester channels. Either writing or reading can be done fully in parallel with no TTO (test time overhead).
Data Wire-OR:
Finally, if both address/data are shared, one can achieve the highest parallelism possible. However, there is a cost involved. In addition to the issues of Address only wire-or, the following issues are encountered.
Signal Performance—Since one cannot disconnect other devices, the signal performance when a given DUT is driving back degrades significantly. There are not only impedance mismatches between the DUT and the transmission line, but also, the other DUT(s) act like stubs which will create other reflections on the signal and therefore limited timing accuracy/data rate.
Parallelism—Similar parallelism loss occurs as in the case of data sharing using switches.
Test Time Overhead—Similar test time overhead occurs as in the case of data sharing using switches.
Thus, the methods described above have either performance limitations or electrical limitations. The use of passive switches provides electrical isolation, but not very good performance. On the other hand a driver wire-OR if done properly could have good performance but won't work at wafer sort due to yield issues. Sharing the data lines increases the parallelism but also adds TTO to perform serial reads. The use of wire-OR is limited to a 2× configuration, since any configuration higher than 2× would significantly increase the manufacturing cost of probe cards or socket boards. Thus, there is a very low limit on what can be done with wire-OR. Finally, some of these options are not well suited for high-frequency testing. For example, most applications of address sharing using relays are running frequencies of less than 100 MHz and OTA (Overall Timing Accuracy) of ˜1 ns.
Thus, there is a need for a system that will permit improvement in testing devices in parallel so as to overcome at least one of the deficiencies currently present in testing systems.